US Patent 7126507 Analog-digital converter using clock boosting

Disclosed herein is an analog-digital converter. The analog-digital converter includes a sample-and-hold amplifier, a first analog-digital converter, a multiple digital-analog converter, a second analog-digital converter, and a digital correction logic. The sample-and-hold amplifier samples an analog input signal using clock boosting. The first analog-digital converter receives a sampled signal, and converts the sampled signal into a plurality of bits of first digital output code. The multiple digital-analog converter receives and stores the sampled signal, and amplifies and outputs the difference between the stored signal and an analog signal corresponding to the first digital output code. The second analog-digital converter receives the output signal of the multiple digital-analog converter, and converts the output signal into a plurality of bits of second digital output code. The digital correction logic receives the first digital output code and the second digital output code, overlaps certain bits of the first digital output code with certain bits of the second digital output code, and outputs remaining bits, exclusive of overlapping bits, as final digital output code.