Patent attributes
A focal plane array in which information from the pixel forming elements is transferred into a vertical shift register and then from the last stage of the vertical shift registers row by row into a horizontal shift register is provided with a storage element and gate between each vertical register and the corresponding stage of the horizontal register. After the information currently in the storage gates has been transferred to the corresponding HCCD stages, the transfer gate is closed, and the next shift of the vertical registers begins, during a time when the vertical registers would otherwise be stopped, waiting for the multi-phase operation of the horizontal register. This time is used for usefully increasing the time for the vertical shift operation, and the clock is advantageously made slower. Alternatively, a faster frame rate can be handled by conventional clock circuits.
