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US Patent 7116743 Digital phase lock loop
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Is a
Patent
Date Filed
March 4, 2004
Date of Patent
October 3, 2006
Patent Application Number
10794080
Patent Citations Received
US Patent 12021960 Maintaining a virtual time of day
0
US Patent 11863299 Shared communication channel that interleaves 1 PPS signals and messaging
0
US Patent 11876607 FSYNC mismatch tracking
0
US Patent 11994896 Maintaining the correct time when counter values are transferred between clock domains
0
US Patent 11664968 Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal
0
US Patent 11671238 Secondary phase compensation assist for PLL IO delay
0
US Patent 11777703 Phase transport with frequency translation without a PLL
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
7116743
Patent Primary Examiner
Timothy P. Callahan
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