US Patent 7116150 Clock gater circuit and associated method

One embodiment is a clock gater circuit comprising an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of the inverter block responsive to a qualifier signal. Also included is circuitry for restoring a logic level at the input node of the inverter block to a particular value, the circuitry operating responsive to the qualifier signal.