US Patent 7116147 Circuit and method for interpolative delay

A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an interpolation circuit, and a differential compare circuit. The differential inverter is coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal. The interpolation circuit is coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal. The differential compare circuit is coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal. The second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.