US Patent 7111112 Semiconductor memory device having control circuit

In a freeze reset circuit in a semiconductor memory device, when a row act signal is not activated in a predetermined period determined by a trailing edge delay circuit after a chip enable signal is set to the H level during a write or read operation, a freeze reset signal is output from a logic gate after a predetermined period. As a result, the semiconductor memory device terminates the write or read operation. Therefore, the semiconductor memory device can ensure the stability of the write or read operation.