Patent attributes
Provided is a digital-analog converter circuit that enables, for example, securing an improved accurate analog signal voltage and preventing increase in the circuit size. A first node of each individual unit is connected to a middle node of a one-order higher unit than a unit having that first node. A second node of the each individual unit is connected to one of the first and second nodes provided in the one-order higher unit than the unit having that second node, the one being on the side connected to a resister section set to an impedance value 2Z. A hierarchical structure can be formed in which an opponent connection point of the second node is selected by a hierarchy switch section, whereby the each individual unit is parallel connected to the resister section provided in the one-order higher unit and set to the impedance value 2Z. In correspondence to an input first-order bit signal (D0), an analog signal voltage (AV) corresponding to an output code (1) of digital data is output from a lowest-order bit unit (LU). In this manner, the D-A conversion operation is performed.
