Patent attributes
A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state. The apparatus further includes means for performing an interpolation, for each DDS accumulator state having a defined transition-state, based upon the value of the preceding DDS accumulator state, means for selecting an element of the set of phase-shifted clock signals based upon the interpolation, and means for repositioning the MSB using the selected element of the phase-shifted clock signals.
