US Patent 7098710 Multi-speed delay-locked loop
Patent 7098710 was granted and assigned to Xilinx on August, 2006 by the United States Patent and Trademark Office.
Is a
Current Assignee
Date Filed
November 21, 2003
Date of Patent
August 29, 2006
Patent Application Number
10719743
Patent Jurisdiction
Patent Number
Patent Primary Examiner
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