US Patent 7088603 DRAM CAM memory

A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and reference bit lines being sensed are each from the same memory array of the CAM device. Noise present in one array therefore appears as common mode noise in both the active and reference bit lines, thereby permitting the sensing operation to be performed accurately even in the presence of increased noise.