US Patent 7057270 Systems and methods for stacking chip components

Systems and methods for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Another embodiment provides a method for stacking chips where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another embodiment is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.