US Patent 7020033 Semiconductor memory apparatus and self-repair method

A memory unit includes unit blocks laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells laid out to form a cell matrix and redundant lines including redundant memory cells each used for repairing an abnormal memory cell. Every plurality of unit blocks forms a two-dimensional group oriented in a first direction and a second direction, and the redundant lines connected in the first and second directions are shared by the unit blocks pertaining to the two-dimensional group. Self-repair means embedded in the same chip as the memory unit stores only a minimum number of address pairs in storage means provided for each of the unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell and, then, finds a redundant line to be used for repairing an abnormal memory cell for each of the unit blocks pertaining to the two-dimensional group on the basis of the address pairs stored in the storage means.