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US Patent 6864127 Semiconductor device and method of fabricating the same

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Patent
Patent
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Patent Applicant
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1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
68641271
Patent Inventor Names
Hideto Ohnuma1
Hisashi Ohtani1
Shunpei Yamazaki1
Tamae Takano1
Date of Patent
March 8, 2005
1
Patent Application Number
103573331
Date Filed
February 4, 2003
1
Patent Citations Received
‌
US Patent 11836277 Secure circuit integrated with memory layer
2
Patent Primary Examiner
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David Nelms
1
Patent abstract

There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).

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