In the display panel, a display region includes a plurality of sub-pixels arranged in an array, and a non-display region includes a plurality of demultiplexers, a plurality of signal source lines and M timing control lines. Each of the plurality of demultiplexers includes N gating switches, where in the same demultiplexer, input terminals of a plurality of gating switches are electrically connected to the same signal source line, an output terminal of each of the plurality of gating switches is electrically connected to one column of sub-pixels, and control terminals of the plurality of gating switches are electrically connected to different timing control lines. data signals transmitted by at least two signal source lines electrically connected to at least two gating switches controlled by a timing control line have opposite voltage polarities.