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US Patent 12087757 Integrated circuit packages

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
June 29, 2023
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Date of Patent
September 10, 2024
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Patent Application Number
18344456
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Patent Citations
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US Patent 9299649 3D packages and methods for forming the same
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US Patent 9372206 Testing of semiconductor chips with microbumps
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US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
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US Patent 9443783 3DIC stacking device and method of manufacture
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US Patent 9461018 Fan-out PoP structure with inconsecutive polymer layer
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US Patent 9496189 Stacked semiconductor devices and methods of forming same
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US Patent 9735131 Multi-stack package-on-package structures
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US Patent 9666502 Discrete polymer in fan-out packages
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US Patent 10672674 Method of forming semiconductor device package having testing pads on a topmost die
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US Patent 8993380 Structure and method for 3D IC package
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•••
Patent Inventor Names
Chung-Hao Tsai
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Chuei-Tang Wang
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Chen-Hua Yu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12087757
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Patent Primary Examiner
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Errol V Fernandes
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CPC Code
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H01L 23/3192
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H01L 25/043
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H01L 22/14
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H01L 25/50
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