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US Patent 12086521 Circuit design simulation and clock event reduction

Patent 12086521 was granted and assigned to Xilinx Inc on September, 2024 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
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Patent attributes

Patent Applicant
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Xilinx Inc
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Current Assignee
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Xilinx Inc
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120865211
Patent Inventor Names
Tharun Kumar Ksheerasagar1
Rohit Bhadana1
Pratyush Ranjan1
Hemant Kashyap1
Date of Patent
September 10, 2024
1
Patent Application Number
174961981
Date Filed
October 7, 2021
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Patent Citations
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US Patent 7636653 Point-to-point ethernet hardware co-simulation interface
1
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US Patent 7673201 Recovering a prior state of a circuit design within a programmable integrated circuit
1
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US Patent 7707019 Command buffering for hardware co-simulation
1
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US Patent 7721090 Event-driven simulation of IP using third party event-driven simulators
1
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US Patent 7739092 Fast hardware co-simulation reset using partial bitstreams
1
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US Patent 7895026 Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling system
1
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US Patent 7930162 Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor
1
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US Patent 8041553 Generic software simulation interface for integrated circuits
1
...
Patent Primary Examiner
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Mohammed Alam
1
Patent abstract

Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

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