US Patent 12079559 IC device layout method
Patent 12079559 was granted and assigned to Taiwan Semiconductor Manufacturing Company on September, 2024 by the United States Patent and Trademark Office.
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US Patent 12079559 IC device layout method
Article
Patent abstract
A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
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Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Guo-Huei Wu0
Hui-Zhong Zhuang0
Jiann-Tyng Tzeng0
Shih-Wei Peng0
Wei-Cheng Lin0
Date of Patent
September 3, 2024
0Patent Application Number
183628890
Date Filed
July 31, 2023
0Patent Citations
Patent Primary Examiner
CPC Code
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