Patent attributes
A processing circuit coupled to an imaging device includes a bus interface circuit configured to communicatively couple the processing circuit to the imaging device over a multidrop differential serial link, detector circuits configured to detect a plurality of sequentially occurring signaling states of the multidrop differential serial link, the plurality of sequentially occurring signaling states related to transmissions of data packets over the multidrop differential serial link, and a controller. The controller is configured to discard data packets received after the imaging device is powered on or initialized and until the imaging device is indicated to be in an active operating state, count sequences of transitions between a first signaling state of the multidrop differential serial link and a second signaling state of the multidrop differential serial link, and indicate that the imaging device is in the active operating state after a preconfigured number of data packets have been discarded.
