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US Patent 12064296 Memory device

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
120642961
Patent Inventor Names
Satoshi Nagashima1
Date of Patent
August 20, 2024
1
Patent Application Number
173244131
Date Filed
May 19, 2021
1
Patent Citations
‌
US Patent 9666594 Multi-charge region memory cells for a vertical NAND device
1
‌
US Patent 10340013 Memory device
1
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US Patent 9147468 Multiple-bit-per-cell, independent double gate, vertical channel memory
1
‌
US Patent 10020315 Semiconductor memory device
1
Patent Primary Examiner
‌
Chuong A Luu
1
CPC Code
‌
H01L 27/1157
1
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H01L 27/11519
1
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H01L 27/11524
1
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H01L 27/11521
1
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H01L 27/11551
1
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H01L 27/11565
1
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H01L 27/11578
1
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H01L 27/11556
1
...
Patent abstract

A memory device includes a first and second conductor respectively included in a first and second layer stack stacked in a first direction and separated from each other; a first and second portion of a semiconductor extending in the first direction between the first and the second layer stack, and separated from each other in same layer; a first film between the first conductor and the first portion; a second film between the second conductor and the second portion; a first insulator between the first conductor and the first film; a second insulator between the second conductor and the second film; a third insulator between the first insulator and the first film; and a fourth insulator between the second insulator and the second film. The third and fourth insulator have a higher dielectric constant than the first and second insulator.

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