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US Patent 12062584 Iterative method of multilayer stack development for device applications

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
120625840
Patent Inventor Names
Sasikanth Manipatruni0
Tanay Gosavi0
Mauricio Manfrini0
Niloy Mukherjee0
Somilkumar J. Rathi0
Debo Olaosebikan0
Rajeev Kumar Dokania0
Noriyuki Sato0
...
Date of Patent
August 13, 2024
0
Patent Application Number
179766890
Date Filed
October 28, 2022
0
Patent Citations
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US Patent 7405959 Ferroelectric memory device
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US Patent 8232189 Dielectric film manufacturing method
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US Patent 8300446 Ferroelectric random access memory with single plate line pulse during read
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US Patent 8441833 Differential plate line screen test for ferroelectric latch circuits
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US Patent 8665628 Ferroelectric memory device
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US Patent 8828194 Layer system that can be annealed and method for producing the same
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US Patent 8865628 Solution for forming rare-earth superconductive film and production method thereof
0
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US Patent 9472560 Memory cell and an array of memory cells
0
...
Patent Primary Examiner
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Jay C Kim
0
CPC Code
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H01L 22/20
0
Patent abstract

A method to deposit a multi-layer stack for device applications includes implementing a model driven target selection for deposition. One or more targets may be procured with an initial stoichiometric composition or elemental purity. The targets may be utilized to form the multi-layer stack, and measurements may be made of chemical composition and electrical properties of the multi-layer stack. The measurements may be compared to reference target values and if measurement results are not within tolerance, the composition of the targets can be changed to yield a successive multi-layer stack. The process can be iterated until measurement results are within tolerance of target results. Additional experimentation with post deposition thermal anneal can be performed to optimize multi-layer stack properties.

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