US Patent 12062112 Apparatus for heterogenous processing

A system on a chip may include a GPU, a CPU, a dedicated memory for the CPU, an FPGA, a dedicated memory for the FPGA, a control and data bus assembly connecting the FPGA, the CPU, and the GPU, wherein the FPGA, the CPU, and the GPU are configured to interact using the control and data bus assembly and an API configured to allow the same code to run on the FPGA, the CPU, and the GPU, a VPX, a first HSIO connection connecting the GPU to the VPX, a second HSIO connection connecting the CPU to the VPX, and a third HSIO connection connecting the FPGA to the VPX.