US Patent 12025661 Power-sensitive scan-chain testing

A method of scan-chain testing of an integrated circuit device having a plurality of respective scan-chain paths, at least some of the respective scan-chain paths being designated as having resource constraints, includes propagating a respective scan-chain data pattern through each of the respective scan-chain paths, and gating each respective scan-chain path designated as having resource constraints, to reduce a rate of scan-chain data propagation through the respective scan-chain path, without gating any scan-chain path not designated as having resource constraints. Scan-chain paths may be designated as having resource constraints because of high power consumption or data congestion.