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US Patent 12021135 Bottom source/drain etch with fin-cut-last-VTFET
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Patent
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Date Filed
May 10, 2023
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Date of Patent
June 25, 2024
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Patent Application Number
18314850
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Patent Citations
US Patent 9530700 Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch
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US Patent 9761727 Vertical FETs with variable bottom spacer recess
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US Patent 9812443 Forming vertical transistors and metal-insulator-metal capacitors on the same chip
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US Patent 9842933 Formation of bottom junction in vertical FET devices
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US Patent 9865705 Vertical field effect transistors with bottom source/drain epitaxy
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US Patent 9935102 Method and structure for improving vertical transistor
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US Patent 9954102 Vertical field effect transistor with abrupt extensions at a bottom source/drain structure
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US Patent 10141446 Formation of bottom junction in vertical FET devices
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US Patent 10141448 Vertical FETs with different gate lengths and spacer thicknesses
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US Patent 10217846 Vertical field effect transistor formation with critical dimension control
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•••
Patent Inventor Names
Eric Miller
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Nelson Felix
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Tao Li
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Indira Seshadri
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12021135
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Patent Primary Examiner
Mohammad M Hoque
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CPC Code
H01L 27/092
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H01L 21/823885
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H01L 21/823814
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H01L 29/0847
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H01L 29/66666
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H01L 29/7827
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H01L 29/0653
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