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US Patent 12002534 Memory array word line routing

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 16, 2022
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Date of Patent
June 4, 2024
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Patent Application Number
17842256
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Patent Citations
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US Patent 9484389 Three-dimensional resistive memory array
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US Patent 9496274 Three-dimensional non-volatile memory device
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US Patent 9570464 Method for manufacturing semiconductor device
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US Patent 9620712 Concave word line and convex interlayer dielectric for protecting a read/write layer
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US Patent 9748257 Semiconductor devices having dummy patterns and methods of fabricating the same
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US Patent 9947721 Thermal insulation for three-dimensional memory arrays
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US Patent 9953992 Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
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US Patent 10056150 Non-volatile semiconductor memory device
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US Patent 10096615 Semiconductor device and method of manufacturing the same
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US Patent 10109639 Lateral non-volatile storage cell
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•••
Patent Inventor Names
Sai-Hooi Yeong
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Meng-Han Lin
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Han-Jong Chia
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Yih Wang
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Yi-Ching Liu
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Chenchen Jacob Wang
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Yu-Ming Lin
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12002534
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Patent Primary Examiner
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Matthew E Warren
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CPC Code
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H01L 29/7869
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H01L 29/78391
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H01L 29/24
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G11C 5/063
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