US Patent 12001696 Channel architecture for memory devices

Systems, apparatuses, and methods related to channel architecture for memory devices are described. Various applications can access data from a memory device via a plurality of channels. The channels can be selectively enabled or disabled based on the behavior of the applications. For instance, an apparatus in the form of a memory system can include an interface coupled to a controller and a plurality of channels. The controller can be configured to determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels and disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of bandwidth used by the plurality of applications.