US Patent 11989144 Centralized interrupt handling for chiplet processing units

Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.