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US Patent 11985825 3D memory array contact structures

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Date Filed
April 15, 2021
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Date of Patent
May 14, 2024
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Patent Application Number
17231523
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Patent Citations
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US Patent 9240420 3D non-volatile storage with wide band gap transistor decoder
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US Patent 10777566 3D array arranged for memory and in-memory sum-of-products operations
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US Patent 10868042 Ferroelectric memory device containing word lines and pass gates and method of forming the same
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US Patent 10998447 Semiconductor device, semiconductor wafer, and electronic device
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US Patent 11011529 Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor
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US Patent 11171157 Method for forming a MFMIS memory device
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US Patent 11205659 Interconnect structures of three-dimensional memory devices
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US Patent 11211395 3D memory array having select lines
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US Patent 11404091 Memory array word line routing
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US Patent 11423966 Memory array staircase structure
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•••
Patent Inventor Names
Yu-Ming Lin
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Feng-Cheng Yang
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Sheng-Chen Wang
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Meng-Han Lin
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Sai-Hooi Yeong
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Han-Jong Chia
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11985825
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Patent Primary Examiner
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Ali Naraghi
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CPC Code
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G11C 8/14
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