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US Patent 11953980 Memory sub-system with dynamic calibration using component-based function(s)

Patent 11953980 was granted and assigned to Micron Technology on April, 2024 by the United States Patent and Trademark Office.

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 US Patent 11953980 Memory sub-system with dynamic calibration using component-based function(s)

Article

Patent abstract

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

Infobox
Is a
Patent
Patent
0
Patent Applicant
Micron Technology
Micron Technology
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Current Assignee
Micron Technology
Micron Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
119539800
Patent Inventor Names
Bruce A. Liikanen0
Gerald L. Cadloni0
Violante Moschiano0
Date of Patent
April 9, 2024
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Patent Application Number
180734020
Date Filed
December 1, 2022
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Patent Citations
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US Patent 11176036 Endurance enhancement scheme using memory re-evaluation
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US Patent 11177006 Memory system with dynamic calibration using a trim management mechanism
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US Patent 7437498 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
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US Patent 8006166 Programming error correction code into a solid state memory device with varying bits per cell
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US Patent 8112064 Function lock information notification method and mobile communication terminal
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US Patent 9092350 Detection and handling of unbalanced errors in interleaved codewords
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US Patent 9117536 Method for operating non-volatile memory device and memory controller
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US Patent 9153336 Decoder parameter estimation using multiple memory reads
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US Patent 9355735 Data recovery in a 3D memory device with a short circuit between word lines
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US Patent 9367391 Error correction operations in a memory device
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US Patent 9454420 Method and system of reading threshold voltage equalization
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US Patent 9472298 Dynamic read valley search in non-volatile memory
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US Patent 9558850 Efficient calibration of a data eye for memory devices
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US Patent 9761308 Systems and methods for adaptive read level adjustment
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US Patent 10140040 Memory device with dynamic program-verify voltage calibration
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US Patent 10170195 Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads
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US Patent 10210926 Tracking of optimum read voltage thresholds in nand flash devices
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US Patent 10276233 Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets
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US Patent 10379739 Data storage device read threshold adjustment according to environmental parameters
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US Patent 10388376 Method for managing the endurance of a non-volatile rewritable memory and device for programming such a memory
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US Patent 10452480 Memory device with dynamic processing level calibration
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US Patent 10521140 Memory device with dynamic program-verify voltage calibration
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US Patent 10566061 Calibrating optimal read levels
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US Patent 10566063 Memory system with dynamic calibration using a trim management mechanism
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US Patent 10664194 Memory system with dynamic calibration using a variable adjustment mechanism
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US Patent 10877827 Read voltage optimization
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US Patent 10936205 Techniques for retention and read-disturb aware health binning
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US Patent 10963327 Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
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US Patent 10990466 Memory sub-system with dynamic calibration using component-based function(s)
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US Patent 11347405 Memory device with dynamic program-verify voltage calibration
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US Patent 11416173 Memory system with dynamic calibration using a variable adjustment mechanism
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Patent Primary Examiner
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Joshua P Lottich
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CPC Code
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G06F 11/079
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G06F 11/0751
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G06F 11/073
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G11C 16/26
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