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US Patent 11953966 Data-driven column-wise clock gating of systolic arrays

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
April 14, 2022
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Date of Patent
April 9, 2024
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Patent Application Number
17721252
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Patent Citations
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US Patent 10517540 Systems and methods to reduce data and complexity in neural signal processing chain
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US Patent 11501145 Memory operation for systolic array
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US Patent 9231674 Method and system for constrained power allocation in the multi-input multi-output systems
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US Patent 11347916 Increasing positive clock skew for systolic array critical path
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Patent Citations Received
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US Patent 12135642 Semiconductor device
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Patent Inventor Names
Fan Wu
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Edith Dallard
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11953966
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Patent Primary Examiner
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Volvick Derose
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CPC Code
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G06F 15/8046
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G06F 1/3237
0

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