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US Patent 11908750 Semiconductor device and method

Patent 11908750 was granted and assigned to Taiwan Semiconductor Manufacturing Company on February, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Date Filed
May 28, 2021
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Date of Patent
February 20, 2024
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Patent Application Number
17333116
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Patent Citations
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US Patent 8962400 In-situ doping of arsenic for source and drain epitaxy
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US Patent 9245805 Germanium FinFETs with metal gates and stressors
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US Patent 9318367 FinFET structure with different fin heights and method for forming the same
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US Patent 9401416 Method for reducing gate height variation due to overlapping masks
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US Patent 9418897 Wrap around silicide for FinFETs
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US Patent 9484346 Semiconductor structure and manufacturing method thereof
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US Patent 9520482 Method of cutting metal gate
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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US Patent 9685533 Transistor with SiCN/SiOCN mulitlayer spacer
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•••
Patent Inventor Names
Shu Ling Liao
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Chung-Chi Ko
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11908750
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Patent Primary Examiner
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Tan N. Tran
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CPC Code
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H01L 21/76829
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H01L 21/823864
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H01L 21/28123
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H01L 21/823814
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H01L 21/823821
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H01L 27/0924
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H01L 29/0653
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H01L 29/0847
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H01L 29/4983
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H01L 29/66545
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•••

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