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US Patent 11894466 Semiconductor device
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Patent
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Date Filed
September 27, 2019
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Date of Patent
February 6, 2024
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Patent Application Number
17279153
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Patent Citations
US Patent 8514340 Method of fabricating array substrate having double-layered patterns
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US Patent 8785242 Semiconductor device and method for manufacturing the same
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US Patent 8956929 Method for manufacturing semiconductor device
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US Patent 9105659 Semiconductor device and method for manufacturing the same
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US Patent 9443876 Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module
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US Patent 9496408 Semiconductor device including oxide semiconductor stack with different ratio of indium and gallium
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US Patent 9608123 Method for manufacturing semiconductor device
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US Patent 9653487 Semiconductor device, manufacturing method thereof, module, and electronic device
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US Patent 9741865 Method of forming semiconductor device including oxide semiconductor stack with different ratio of indium and gallium
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US Patent 9899536 Method of forming semiconductor device with different energy gap oxide semiconductor stacked layers
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•••
Patent Inventor Names
Takashi Shiraishi
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Yasutaka Nakazawa
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Rai Sato
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Masami Jintyou
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Satoru Saito
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Masayoshi Dobashi
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11894466
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Patent Primary Examiner
David A Zarneke
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CPC Code
H01L 2029/42388
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H01L 29/7869
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H01L 29/4908
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H01L 29/78621
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