US Patent 11885837 Ultra-low leakage test verification circuit

A test verification circuit is described herein for verifying proper operation of a tested circuit, such as a voltage hazard warning circuit, using an N-channel MOSFET configured for switching ON and OFF the test verification circuit during a power outage, and a voltage source that provides an input voltage to the N-channel MOSFET from a conserved power supply. The N-channel MOSFET provides temporary power from a conserved power supply to the test verification circuit upon activation by a user during a power outage, and the test verification circuit determines whether the tested circuit has been de-energized, remains energized, or there remains inadequate power to complete the test.