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US Patent 11881454 Stacked IC structure with orthogonal interconnect layers

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
118814541
Patent Inventor Names
Ilyas Mohammed1
Steven L. Teig1
Javier A. Delacruz1
Date of Patent
January 23, 2024
1
Patent Application Number
172017321
Date Filed
March 15, 2021
1
Patent Citations
‌
US Patent 10672743 3D Compute circuit with high density z-axis interconnects
1
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US Patent 11355404 Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
1
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US Patent 11355443 Dielets on flexible and stretchable packaging for microelectronics
1
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US Patent 11367652 Microelectronic assembly from processed substrate
1
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US Patent 11373963 Protective elements for bonded structures
1
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US Patent 11380597 Bonded structures
1
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US Patent 11385278 Security circuitry for bonded structures
1
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US Patent 11387202 Nanowire bonding interconnect for fine-pitch microelectronics
1
...
Patent Primary Examiner
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Brook Kebede
1
CPC Code
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H01L 24/26
1
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H01L 25/0657
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H01L 23/5225
1
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H01L 23/50
1
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H01L 23/528
1
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H01L 27/0688
1
Patent abstract

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

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