Log in
Sign up
Golden has been acquired by ComplyAdvantage.Read about it here ⟶
‌

US Patent 11875874 Data structures with multiple read ports

Patent 11875874 was granted and assigned to Groq on January, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity

All edits

Edits on 19 Jan, 2024
"Created via: Patent importer"
Golden AI profile picture
Golden AI
created this topic on 19 Jan, 2024
Edits made to:
Infobox (+61 properties)
Article (+42 characters)
‌

 US Patent 11875874 Data structures with multiple read ports

Article

Patent abstract

A memory structure having 2

Infobox
Is a
Patent
Patent
0
Patent Applicant
Groq
Groq
0
Current Assignee
Groq
Groq
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
118758740
Patent Inventor Names
Gregory M. Thorson0
Jonathan Alexander Ross0
Date of Patent
January 16, 2024
0
Patent Application Number
173971580
Date Filed
August 9, 2021
0
Patent Citations
‌
US Patent 11086623 Systems, methods, and apparatuses for tile matrix multiplication and accumulation
0
‌
US Patent 7181484 Extended-precision accumulation of multiplier output
0
‌
US Patent 7236995 Data processing apparatus and method for converting a number between fixed-point and floating-point representations
0
‌
US Patent 7272730 Application-driven method and apparatus for limiting power consumption in a processor-controlled hardware platform
0
‌
US Patent 7339941 Connecting ethernet based system on a chip integrated circuits in a ring topology
0
‌
US Patent 7421559 Apparatus and method for a synchronous multi-port memory
0
‌
US Patent 7640528 Hardware acceleration of functional factoring
0
‌
US Patent 7805392 Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table
0
‌
US Patent 7861060 Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
0
‌
US Patent 7912889 Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication
0
‌
US Patent 7965725 Hyper-ring-on-chip (HyRoC) architecture
0
‌
US Patent 8038539 Constant-velocity joint with torque-combining differential
0
‌
US Patent 8089959 Method and apparatus to schedule packets through a crossbar switch with delay guarantees
0
‌
US Patent 8250555 Compiling code for parallel processing architectures based on control flow
0
‌
US Patent 8286172 Systems and methods for implementing best-effort parallel computing frameworks
0
‌
US Patent 8345540 Virtual snooping bridge in computer networks
0
‌
US Patent 8370280 Combining predictive models in predictive analytical modeling
0
‌
US Patent 8407167 Method for optimizing memory controller configuration in multi-core processors using fitness metrics and channel loads
0
‌
US Patent 8583895 Compressed instruction format for use in a VLIW processor
0
‌
US Patent 8655937 High precision integer division using low precision hardware operations and rounding techniques
0
‌
US Patent 8689202 Scheduling of instructions
0
‌
US Patent 8830993 Extensible time space switch systems and methods for high capacity multi-service applications
0
‌
US Patent 8850262 Inter-processor failure detection and recovery
0
‌
US Patent 8989220 High speed variable bandwidth ring-based system
0
‌
US Patent 9009660 Programming in a multiprocessor environment
0
‌
US Patent 9146747 Apparatus, systems, and methods for providing configurable computational imaging pipeline
0
‌
US Patent 9388862 Constant velocity universal joint for helicopter rotor
0
‌
US Patent 9432298 System, method, and computer program product for improving memory systems
0
‌
US Patent 9442757 Data parallel computing on multiple processors
0
‌
US Patent 9535869 Method and apparatuses for respectively transferring information within and between system-on-chips (SOCS) via an internal bus and an external bus according to the same communication protocol
0
‌
US Patent 9639490 Ring protocol for low latency interconnect switch
0
‌
US Patent 9672188 Optimization of loops and data flow sections in multi-core processor environment
0
‌
US Patent 9690938 Methods and apparatus for machine learning based malware detection
0
‌
US Patent 9691019 Depth concatenation using a matrix computation unit
0
‌
US Patent 9697463 Computing convolutions using a neural network processor
0
‌
US Patent 9710265 Neural network compute tile
0
‌
US Patent 9710748 Neural network processor
0
‌
US Patent 9723317 Method of generating media file and storage medium storing media file generation program
0
‌
US Patent 9805303 Rotating data for neural network computations
0
‌
US Patent 10167800 Hardware node having a matrix vector unit with block-floating point processing
0
‌
US Patent 10175980 Neural network compute tile
0
‌
US Patent 10235735 Graphics processor with tiled compute kernels
0
‌
US Patent 10320390 Field programmable gate array including coupled lookup tables
0
‌
US Patent 10489680 Efficient data layouts for convolutional neural networks
0
‌
US Patent 10521488 Dynamic partitioning
0
‌
US Patent 10754621 Tiled switch matrix data permutation circuit
0
‌
US Patent 10776110 Apparatus and method for adaptable and efficient lane-wise tensor processing
0
‌
US Patent 10936569 Efficient and scalable computations with sparse tensors
0
‌
US Patent 6988181 VLIW computer processing architecture having a scalable number of register files
0
‌
US Patent 7015913 Method and apparatus for multithreaded processing of data in a programmable graphics processor
0
Patent Primary Examiner
‌
Stephanie Wu
0

Find more entities like US Patent 11875874 Data structures with multiple read ports

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo
By using this site, you agree to our Terms of Service.