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US Patent 11868621 Data storage with multi-level read destructive memory

Patent 11868621 was granted and assigned to Seagate Technology on January, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Seagate Technology
Seagate Technology
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Current Assignee
Seagate Technology
Seagate Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118686210
Patent Inventor Names
Jon D. Trantham0
Darshana H. Mehta0
Mohamad El-Batal0
Praveen Viraraghavan0
Sangita Shreedharan Kalarickal0
John W. Dykes0
Matthew J. Totin0
Ian J. Gilbert0
Date of Patent
January 9, 2024
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Patent Application Number
178441740
Date Filed
June 20, 2022
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Patent Citations
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US Patent 9430735 Neural network in a memory device
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US Patent 10038092 Three-level ferroelectric memory cell using band alignment engineering
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US Patent 11048643 Nonvolatile memory controller enabling wear leveling to independent zones or isolated regions
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US Patent 10797237 Resistive memory architectures with multiple memory cells per access device
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US Patent 6914853 Mechanism for efficient wearout counters in destructive readout memory
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US Patent 7372718 Storage and semiconductor device
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US Patent 8315081 Memory cell that includes multiple non-volatile memories
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US Patent 8422303 Early degradation detection in flash memory using test cells
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...
Patent Primary Examiner
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William E. Baughman
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CPC Code
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G06F 3/0679
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G11C 11/5657
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G06F 3/0616
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G06F 3/0653
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G11C 29/08
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Patent abstract

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

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