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US Patent 11868253 Memory device interface and method

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
July 11, 2022
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Date of Patent
January 9, 2024
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Patent Application Number
17861627
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Patent Citations
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US Patent 8069379 Memory system with point-to-point request interconnect
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US Patent 8275936 Load reduction system and method for DIMM-based memory systems
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US Patent 8543758 Apparatus including memory channel control circuit and related methods for relaying commands to logical units
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US Patent 8754533 Monolithic three-dimensional semiconductor device and structure
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US Patent 8984189 Systems, methods, and apparatuses for stacked memory
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US Patent 9357649 276-pin buffered memory card with enhanced memory system interconnect
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US Patent 9378707 Gamma voltage generation unit and display device using the same
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US Patent 9391048 Semiconductor package
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US Patent 9489009 System on chip, bus interface and method of operating the same
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US Patent 9519315 276-pin buffered memory card with enhanced memory system interconnect
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•••
Patent Inventor Names
Matthew B. Leslie
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Owen Fay
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Chan H. Yoo
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Roy E. Greeff
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Brent Keeth
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11868253
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Patent Primary Examiner
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Pho M Luu
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CPC Code
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G11C 2211/4062
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G11C 29/12
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G11C 11/4093
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G06F 12/0215
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