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US Patent 11842169 Systolic multiply delayed accumulate processor architecture

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
September 25, 2019
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Date of Patent
December 12, 2023
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Patent Application Number
16582918
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Patent Citations
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US Patent 8924455 Multiplication of matrices using systolic arrays
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US Patent 10790830 Fused memory and arithmetic circuit
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US Patent 10817260 Reducing dynamic power consumption in arrays
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US Patent 10872295 Residual quantization of bit-shift weights in an artificial neural network
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US Patent 10879904 Application specific integrated circuit accelerators
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US Patent 10915297 Hardware accelerator for systolic matrix multiplication
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US Patent 11113233 Multiple busses in a grouped systolic array
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US Patent 11232062 Parallelism within a systolic array using multiple accumulate busses
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US Patent 11308026 Multiple busses interleaved in a systolic array
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US Patent 11422773 Multiple busses within a systolic array processing element
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•••
Patent Citations Received
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US Patent 12067375 Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
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Patent Inventor Names
Thomas Elmer
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11842169
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Patent Primary Examiner
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Shawn Doman
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CPC Code
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G06F 9/30076
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G06F 9/30101
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G06F 9/3869
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G06F 9/3893
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G06F 15/8046
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G06F 7/501
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G06F 9/30069
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G06F 7/5443
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