US Patent 11791804 Circuit for generating bias signal and clock input circuit

Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.