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US Patent 11791270 Direct bonded heterogeneous integration silicon bridge
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Patent
Date Filed
May 10, 2021
Date of Patent
October 17, 2023
Patent Application Number
17315859
Patent Citations
US Patent 8064224 Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US Patent 8227904 Multi-chip package and method of providing die-to-die interconnects in same
US Patent 9330946 Method and structure of die stacking using pre-applied underfill
US Patent 9357646 Package substrate
US Patent 9368450 Integrated device package comprising bridge in litho-etchable layer
US Patent 9373559 Low-stress dual underfill packaging
US Patent 9653428 Semiconductor package and fabricating method thereof
US Patent 9860996 Selective area heating for 3D chip stack
US Patent 9865569 Planarity-tolerant reworkable interconnect with integrated testing
US Patent 9875986 Micro-scrub process for fluxless micro-bump bonding
•••
Patent Inventor Names
Paul S. Andry
Pascale Gagnon
Vijayeshwar Das Khanna
Kamal K Sikka
Marc A. Bergendahl
Maryse Cournoyer
Hiroyuki Mori
Dale Curtis McHerron
Ravi K. Bonam
Isabel De Sousa
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11791270
Patent Primary Examiner
William A Harriston
CPC Code
H01L 23/5381
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