Log in
Enquire now
‌

US Patent 11783875 Circuits and methods for in-memory computing

OverviewStructured DataIssuesContributors

Contents

Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11783875
Patent Inventor Names
Zhewei Jiang
Shihui Yin
Mingoo Seok
Jae-sun Seo
Date of Patent
October 10, 2023
Patent Application Number
17828964
Date Filed
May 31, 2022
Patent Citations
‌
US Patent 8716081 Capacitor top plate over source/drain to form a 1T memory device
‌
US Patent 8787102 Memory device and signal processing circuit
‌
US Patent 9001549 Semiconductor device
‌
US Patent 9276091 Semiconductor device and method for manufacturing the same
‌
US Patent 9514816 Non-volatile static RAM and method of operation thereof
‌
US Patent 10012929 Imaging cartridge chip, imaging cartridge, and method for switching imaging cartridge chip serial number
‌
US Patent 10636481 Memory cell for computing-in-memory applications, memory unit for computing-in-memory applications and computing method thereof
‌
US Patent 10121533 Techniques for data retention in memory cells during power interruption
...
Patent Citations Received
Loading...
1
Patent Primary Examiner
‌
Son L. Mai
CPC Code
‌
G06F 7/5443
‌
G11C 15/043
‌
G11C 15/04
‌
G11C 7/1078
‌
G11C 7/1051
‌
G06F 7/501
‌
G11C 7/1036
Patent abstract

In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

Timeline

No Timeline data yet.

Further Resources

Title
Author
Link
Type
Date
No Further Resources data yet.

References

Find more entities like US Patent 11783875 Circuits and methods for in-memory computing

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo

Company

  • Home
  • Press & Media
  • Blog
  • Careers
  • WE'RE HIRING

Products

  • Knowledge Graph
  • Query Tool
  • Data Requests
  • Knowledge Storage
  • API
  • Pricing
  • Enterprise
  • ChatGPT Plugin

Legal

  • Terms of Service
  • Enterprise Terms of Service
  • Privacy Policy

Help

  • Help center
  • API Documentation
  • Contact Us
By using this site, you agree to our Terms of Service.