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US Patent 11755509 Deterministic operation of storage class memory

Patent 11755509 was granted and assigned to Rambus on September, 2023 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Rambus
Rambus
Current Assignee
Rambus
Rambus
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11755509
Patent Inventor Names
Brent Haukness
Frederick A. Ware
Date of Patent
September 12, 2023
Patent Application Number
17715404
Date Filed
April 7, 2022
Patent Citations
‌
US Patent 8300477 Piecewise erasure of flash memory
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US Patent 8645617 Memory device for concurrent and pipelined memory operations
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US Patent 9093160 Methods and systems for staggered memory operations
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US Patent 9158672 Dynamic deterministic address translation for shuffled memory spaces
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US Patent 9785360 Adaptive and dynamic mixed read/write input/output balancer
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US Patent 9710226 Unsuccessful write retry buffer
‌
US Patent 7093071 Queued copy command
‌
US Patent 7100020 Digital communications processor
...
Patent Primary Examiner
‌
Yaima Rigol

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

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