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US Patent 11716847 Three-dimensional NAND memory device with split gates

Overview Structured Data Issues Contributors

Is a

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Date of Patent

August 1, 2023

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Patent Application Number

171136241

Date Filed

December 7, 2020

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Patent Citations

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1

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US Patent 10090318 Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure

1

US Patent 10103165 Memory device

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US Patent 10497711 Non-volatile memory with reduced program speed variation

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US Patent 10276583 Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof

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US Patent 10566346 Vertical-type memory device

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...

Patent Primary Examiner

Mary A Wilczewski

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CPC Code

1

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A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

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