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US Patent 11715546 Memory array test method and system

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Date Filed
August 10, 2022
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Date of Patent
August 1, 2023
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
17884634
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Patent Citations
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US Patent 9256709 Method for integrated circuit mask patterning
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US Patent 9455038 Storage module and method for using healing effects of a quarantine process
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US Patent 9478315 Bit error rate mapping in a memory system
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US Patent 9613715 Low-test memory stack for non-volatile storage
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US Patent 9672934 Temperature compensation management in solid-state memory
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US Patent 9870822 Non-volatile memory element with thermal-assisted switching control
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US Patent 10216571 System and methodology for error management within a shared non-volatile memory architecture using bloom filters
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US Patent 10254982 System and methodology for low latency error management within a shared non-volatile memory architecture
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US Patent 10489086 Reducing read errors by performing mitigation reads to blocks of non-volatile memory
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US Patent 10658577 Maintaining coercive field after high temperature anneal for magnetic device applications with perpendicular magnetic anisotropy
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•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11715546
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Patent Primary Examiner
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Esaw T Abraham
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CPC Code
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G11C 11/1655
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G11C 29/10
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G11C 29/38
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G11C 29/04
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G11C 29/026
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G11C 29/46
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G11C 11/1697
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