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US Patent 11714752 Nonvolatile physical memory with DRAM cache

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Rambus
Rambus
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Date Filed
March 23, 2022
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Date of Patent
August 1, 2023
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Patent Applicant
Rambus
Rambus
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Patent Application Number
17702505
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Patent Citations
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US Patent 8250328 Apparatus and method for buffered write commands in a memory
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US Patent 8300477 Piecewise erasure of flash memory
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US Patent 8427891 Hybrid volatile and non-volatile memory device with a shared interface circuit
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US Patent 8554982 Storage device and information processing system
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US Patent 8645617 Memory device for concurrent and pipelined memory operations
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US Patent 8694716 Method for writing and reading data in an electrically erasable and programmable nonvolatile memory
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US Patent 8745315 Memory Systems and methods supporting volatile and wear-leveled nonvolatile physical memory
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US Patent 8874827 Page merging for buffer efficiency in hybrid memory systems
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US Patent 8914568 Hybrid memory architectures
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US Patent 9158672 Dynamic deterministic address translation for shuffled memory spaces
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•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11714752
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Patent Primary Examiner
Charles Rones
Charles Rones
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CPC Code
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G06F 2212/1044
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G06F 12/0804
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G11C 14/0018
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G06F 2212/205
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G06F 12/12
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