US Patent 11705725 Integrated circuit with electrostatic discharge protection

An integrated circuit includes a signal pad, receiving an input signal during a normal mode, and receive an ESD signal during an ESD mode; an internal circuit, processing the input signal during the normal mode; a variable impedance circuit, comprising a first end coupled to the signal pad, a second end coupled to the internal circuit, wherein the variable impedance circuit provides a low or high impedance path between the signal pad and the internal circuit during the normal or ESD mode; and a switch circuit, comprising a first end coupled to a control end of the variable impedance circuit, a second end coupled to a reference voltage terminal, and a control end receiving a node voltage, wherein the switch circuit switches the control end of the variable impedance circuit to have a first specific voltage or be electrically floating during the normal or ESD mode.