US Patent 11669302 In-memory bit-serial addition system
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US Patent 11669302 In-memory bit-serial addition system
Article
An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (C
Infobox
Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
116693020
Date of Patent
June 6, 2023
0Patent Application Number
170719300
Date Filed
October 15, 2020
0Patent Citations
Patent Primary Examiner
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