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US Patent 11647634 Three-dimensional memory device and method

Overview Structured Data Issues Contributors

Is a

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Date Filed

September 11, 2020

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Date of Patent

May 9, 2023

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Patent Application Number

17018114

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Patent Citations

US Patent 10256248 Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

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US Patent 10283513 Three-dimensional memory device with annular blocking dielectrics and method of making thereof

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US Patent 10446437 Interlevel connectors in multilevel circuitry, and method for forming the same

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US Patent 10593399 Self-selecting memory array with horizontal bit lines

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US Patent 11011529 Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor

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US Patent 10930333 Embedded ferroelectric memory cell

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US Patent 11355516 Three-dimensional memory device and method

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US Patent 10109639 Lateral non-volatile storage cell

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US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

1

Patent Primary Examiner

S M Sohel Imtiaz

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CPC Code

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