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US Patent 11532640 Method for manufacturing a three-dimensional memory

Overview Structured Data Issues Contributors Activity

Is a

Patent

Date Filed

September 4, 2020

Date of Patent

December 20, 2022

Patent Application Number

17012848

Patent Citations

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US Patent 10256248 Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

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US Patent 10446437 Interlevel connectors in multilevel circuitry, and method for forming the same

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US Patent 10593399 Self-selecting memory array with horizontal bit lines

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US Patent 11011529 Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor

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US Patent 10930333 Embedded ferroelectric memory cell

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US Patent 11355516 Three-dimensional memory device and method

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US Patent 10109639 Lateral non-volatile storage cell

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US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same

Patent Inventor Names

Feng-Cheng Yang

Sheng-Chen Wang

Meng-Han Lin

Han-Jong Chia

Chung-Te Lin

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

11532640

Patent Primary Examiner

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Herve-Louis Y Assouman

CPC Code

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