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US Patent 11520717 Memory tiles in data processing engine array

Patent 11520717 was granted and assigned to Xilinx on December, 2022 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
Xilinx
Xilinx
Date Filed
March 9, 2021
Date of Patent
December 6, 2022
Patent Applicant
Xilinx
Xilinx
Patent Application Number
17196669
Patent Citations
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US Patent 10824584 Device with data processing engine array that enables partial reconfiguration
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US Patent 10838908 Configurable network-on-chip for a programmable device
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US Patent 10866753 Data processing engine arrangement in a device
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US Patent 11336287 Data processing engine array architecture with memory tiles
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US Patent 10963421 Flexible address mapping for a NoC in an integrated circuit
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US Patent 10243882 Network on chip switch interconnect
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US Patent 10505548 Multi-chip structure having configurable network-on-chip
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US Patent 10673439 Adaptive integrated programmable device platform
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US Patent 10747690 Device with data processing engine array
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US Patent 10824505 ECC proxy extension and byte organization for multi-master systems
Patent Citations Received
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US Patent 12001369 Broadcast regions for multi-processor arrangement
0
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US Patent 11874793 Broadcast hub for multi-processor arrangement
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11520717
Patent Primary Examiner
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Michael Sun

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