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US Patent 11515202 3D IC method and device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
May 7, 2021
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Date of Patent
November 29, 2022
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Patent Application Number
17315166
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Patent Citations
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US Patent 10446456 Integrated circuits protected by substrates with cavities, and methods of manufacture
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US Patent 10707087 Processing stacked substrates
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US Patent 10790262 Low temperature bonded structures
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US Patent 10879212 Processed stacked dies
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US Patent 10964664 DBI to Si bonding for simplified handle wafer
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US Patent 10998292 Offset pads over TSV
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US Patent 11011418 3D IC method and device
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US Patent 11031285 Diffusion barrier collar for interconnects
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US Patent 11056348 Bonding surfaces for microelectronics
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US Patent 11069734 Image sensor device
•••
Patent Inventor Names
Gaius Gillman Fountain, Jr.
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Paul M. Enquist
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Qin-Yi Tong
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11515202
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Patent Primary Examiner
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David Vu
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CPC Code
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H01L 2924/01022
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H01L 2924/01023
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H01L 2924/01027
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H01L 2924/01028
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H01L 2924/01029
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H01L 2924/01033
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H01L 2924/01042
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H01L 2924/01046
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H01L 2924/01049
0
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H01L 2924/0105
0
•••

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